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CY62157EV18 MoBL(R)
8-Mbit (512K x 16) Static RAM
Features
* Very high speed: 55 ns * Wide voltage range: 1.65V-2.25V * Pin Compatible with CY62157DV18 and CY62157DV20 * Ultra low standby power -- Typical Standby current: 2 A -- Maximum Standby current: 8 A * Ultra low active power -- Typical active current: 1.8 mA @ f = 1 MHz * Easy memory expansion with CE1, CE2 and OE features * Automatic power down when deselected * CMOS for optimum speed and power * Available in Pb-free 48-ball VFBGA package deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: * Deselected (CE1 HIGH or CE2 LOW) * Outputs are disabled (OE HIGH) * Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or * Write operation is active (CE1 LOW, CE2 HIGH and WE LOW). Write to the device by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). Read from the device by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes.
Functional Description [1]
The CY62157EV18 is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. The device can also be put into standby mode when
Product Portfolio
Power Dissipation Product VCC Range (V) Speed (ns) Max 2.25 55 Typ [2] 1.8 Operating ICC, (mA) f = 1MHz Min CY62157EV18 1.65 Typ [2] 1.8 Max 3 f = fmax Typ [2] 18 Max 25 Standby, ISB2 (A) Typ [2] 2 Max 8
Notes 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" located at http://www.cypress.com. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
Cypress Semiconductor Corporation Document #: 38-05490 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 30, 2007
CY62157EV18 MoBL(R)
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
512K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE
A11 A12 A13
A15
A14
A16
A17 A18
CE2 CE1
OE BLE
POWER DOWN CIRCUIT
BHE BLE CE2 CE1
Pin Configuration [3]
48-ball VFBGA Top View
1 BLE IO8 IO9 VSS VCC IO14 IO15 A18 2 OE BHE IO10 IO11 IO12 IO13 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 IO1 IO3 IO4 IO5 WE A11 6 CE2 IO0 IO2 VCC VSS IO6 IO7 NC A B C D E F G H
Note 3. NC pins are not connected on the die.
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CY62157EV18 MoBL(R)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential ...............................-0.2V to 2.45V (VCCmax + 0.2V) DC Voltage Applied to Outputs in High-Z State [4, 5] ..............-0.2V to 2.45V (VCCmax + 0.2V) DC Input Voltage [4, 5] ......... -0.2V to 2.45V (VCCmax + 0.2V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ......................................... > 2001V (in accordance with MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA
Operating Range
Device Range Ambient Temperature VCC [6]
CY62157EV18LL Industrial -40C to +85C 1.65V to 2.25V
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V to 2.25V VCC = 1.65V to 2.25V GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels Test Conditions VCC = 1.65V VCC = 1.65V 1.4 -0.2 -1 -1 18 1.8 2 55 ns Min 1.4 0.2 VCC + 0.2V 0.4 +1 +1 25 3 8 Typ [2] Max Unit V V V V A A mA mA A
ISB1
Automatic CEPower Down CE1 > VCC-0.2V or CE2 < 0.2V Current-CMOS Inputs VIN > VCC - 0.2V, VIN < 0.2V) f = fmax (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = VCC(max). Automatic CE Power Down CE1 > VCC - 0.2V or CE2 < 0.2V, Current-CMOS Inputs VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max).
ISB2 [7]
2
8
A
Capacitance [8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.5V for pulse durations less than 20 ns. 6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 spec. Other inputs can be left floating. 8. Tested initially and after any design or process changes that may affect these parameters.
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CY62157EV18 MoBL(R)
Thermal Resistance [8]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 72 8.86 Unit C/W C/W
AC Test Loads and Waveforms
VCC OUTPUT R1 3V 30 pF INCLUDING JIG AND SCOPE R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH OUTPUT V Value 13500 10800 6000 0.80 Unit V
Parameters R1 R2 RTH VTH
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR [8] tR [9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC= VDR, CE1 > VCC - 0.2V, CE2 < 0.2V,VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min 1.0 1 3 Typ [2] Max Unit V A ns ns
Data Retention Waveform [10]
DATA RETENTION MODE VCC CE1 or BHE.BLE or CE2
VCC(min) tCDR
VDR > 1.0V
VCC(min) tR
Notes 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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CY62157EV18 MoBL(R)
Switching Characteristics (Over the Operating Range) [11, 12]
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[16] [15]
Description
55 ns Min 55 55 10 55 25 5 18
[13] [13, 14]
Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z
[13] [13, 14]
ns ns ns ns ns ns ns ns 18 ns ns 55 55 ns ns ns 18 ns ns ns ns ns ns ns ns ns ns 18 ns ns
OE HIGH to High-Z
CE1 LOW and CE2 HIGH to Low-Z CE1 HIGH and CE2 LOW to High-Z
10 0
CE1 LOW and CE2 HIGH to Power Up CE1 HIGH and CE2 LOW to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low-Z
[13] [13, 14]
10
BLE/BHE HIGH to High-Z Write Cycle Time
45 35 35 0 0 35 35 25 0
CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z WE HIGH to Low-Z
[13, 14] [13]
10
Notes 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state. 15. If both byte enables are toggled together, this value is 10 ns. 16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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CY62157EV18 MoBL(R)
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [17, 18]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle 2 (OE Controlled) [18, 19]
ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU
50%
50%
ICC ISB
Notes: 17. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 18. WE is HIGH for read cycle. 19. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05490 Rev. *D
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CY62157EV18 MoBL(R)
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) [16, 20, 21]
tWC ADDRESS tSCE CE1 CE2 tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 22 tHZOE VALID DATA
tHD
Write Cycle 2 (CE1 or CE2 Controlled) [16, 20, 21]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE
BHE/BLE
tBW
OE tSD DATA IO NOTE 22 tHZOE
Notes: 20. Data IO is high impedance if OE = VIH. 21. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 22. During this period, the IOs are in output state and input signals must not be applied.
tHD
VALID DATA
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CY62157EV18 MoBL(R)
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW) [21]
tWC ADDRESS tSCE CE1 CE2
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATA IO NOTE 22 VALID DATA
tHD
tHZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW) [21]
tWC ADDRESS
tLZWE
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 22 VALID DATA tHD tBW tHA
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CY62157EV18 MoBL(R)
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High-Z High-Z High-Z Data Out (IO0-IO15) Data Out (IO0-IO7); High-Z (IO8-IO15) High-Z (IO0-IO7); Data Out (IO8-IO15) High-Z High-Z High-Z Data In (IO0-IO15) Data In (IO0-IO7); High-Z (IO8-IO15) High-Z (IO0-IO7); Data In (IO8-IO15) Mode Deselect/Power Down Deselect/Power Down Deselect/Power Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62157EV18LL-55BVXI Package Diagram Package Type Operating Range Industrial
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Contact your local Cypress sales representative for availability of these parts
Document #: 38-05490 Rev. *D
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CY62157EV18 MoBL(R)
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C 1.00 MAX
SEATING PLANE 0.26 MAX. C
51-85150-*D
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05490 Rev. *D
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157EV18 MoBL(R)
Document History
Document Title: CY62157EV18 MoBL(R) 8-Mbit (512K x 16) Static RAM Document Number:38-05490 REV. ECN NO. Issue Date ** *A 202862 291272 See ECN See ECN Orig. of Change AJU SYT New Data Sheet Converted from Advance Information to Preliminary Changed VCC Max from 2.20 to 2.25 V Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed ICCDR from 4 to 4.5 A Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bins Changed tDOE from 15 and 22 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns Speed Bins respectively Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Changed tSCE, tAW, and tBW from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns Speed Bins respectively Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns Speed Bins respectively Added Pb-Free Package Information Converted from Preliminary to Final Removed 35 ns speed bin Removed "L" bin Changed ball E3 from DNU to NC Removed redundant footnote on DNU Modified Maximum Ratings spec for Supply Voltage and DC Input Voltage from 2.4V to 2.45V Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA to 25 mA for test condition f = fax = 1/tRC Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz Changed the ISB1 and ISB2 Max value from 4.5 A to 8 A and Typ value from 0.9 A to 2 A respectively Updated Thermal Resistance table Changed Test Load Capacitance from 50 pF to 30 pF Added Typ value for ICCDR Changed the ICCDR Max value from 4.5 A to 3 A Corrected tR in Data Retention Characteristics from 100 s to tRC ns Changed tLZOE from 3 to 5 Changed tLZCE from 6 to 10 Changed tHZCE from 22 to 18 Changed tLZBE from 6 to 5 Changed tPWE from 30 to 35 Changed tSD from 22 to 25 Changed tLZWE from 6 to 10 Added footnote #13 Updated the ordering Information and replaced the Package Name column with Package Diagram Replaced 45ns speed bin with 55ns Description of Change
*B
444306
See ECN
NXR
*C
571786
See ECN
VKN
Document #: 38-05490 Rev. *D
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CY62157EV18 MoBL(R)
Document Title: CY62157EV18 MoBL(R) 8-Mbit (512K x 16) Static RAM Document Number:38-05490 REV. ECN NO. Issue Date *D 908120 See ECN Orig. of Change VKN Description of Change Added footnote #7 related to ISB2 Added footnote #12 related AC timing parameters
Document #: 38-05490 Rev. *D
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